Programming FPGAs the Old-Fashioned Way

HDL vs. OpenCL – how to choose?

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With all the hoopla over programming Field Programmable Gate Arrays (FPGAs) using OpenCL, you might think that HDL programming (Verilog or VHDL) for FPGAs was dead. The reality is that OpenCL opens new ways to program FPGAs, but it doesn’t replace the old tried and true HDL programming methods. It’s another case of using the right tool for the right job.

Why do we need HDLs when we have OpenCL?

FPGAs are essentially a bunch of circuits, wires, and pins ready to be wired. When we think of them that way, then Verilog or VHDL is the way to go.  A newer view of FPGAs has them function as application accelerators. (I discussed this recently in “FPGAs and OpenCL: What’s Up?”) When thinking of FPGAs as accelerators for computation, OpenCL is the way to go. OpenCL handles many details, such as memory usage and I/O, in a standard way that allows us to focus on acceleration of computation.

However, when we want to play with output pins to control things, or blink LEDs on a board, OpenCL is not the way to go. OpenCL enthusiasts may point out that OpenCL “could” be set up to blink LEDs (just provide for it in the board support package, or embed some Verilog). While technically true, the current board support packages don’t bother to try to support such usage because it is simply not why OpenCL is used with FPGAs.

Blinking some LEDs

C programmers start by writing a program, known as “hello world,” to type out “Hello, World!”  FPGA programmers start by writing a program, known as “blinky,” to blink an LED.

My deluxe version of “blinky” does a sequential turn signal. Sequential turn signals were first factory fitted to 1965–1971 model year Ford Thunderbirds and have been affectionately referred to as “T-Bird turn signals.”

I’ve implemented T-Bird turn signals on numerous FPGA development boards using a combination of an HDL (Verilog or VHDL) and schematics. The most basic way to program an FPGA would involve only HDL. More advanced tools allow for drawing schematics and combining them with HDL.

A quick look at schematics and Verilog code

To show both schematics and Verilog and programming, I will share my implementation for a DE0-nano-SoC kit.  This will give you a characteristic glimpse into what this style of programming looks like.

The DE0-SoC Development Kit features an Altera Cyclone V SoC with 49K logical elements (that’s the “FPGA” portion) plus an integrated dual-core ARM Cortex A9 Processor. Note that the “DE0” name has been used for boards based on Cyclone III, IV, or V SoCs. The board also has 3.3V Arduino shield compatibility via female headers, 1 Gig of external DDR3 SDRAM, and support for Gigabit Ethernet.

The circuit is actually very simple. Here’s the schematic I drew in the Quartus Prime tools from Intel/Altera (the free “Lite” version supports this board completely):

intell image 11 James Reinders

Schematic for my deluxe blinky project, using Quartus Prime tools, for the DE0-nano-SoC board

I got fancy and used the keys on the board to click on/off the right or left turn signals. The circuit has three parts: (top) a clock is used to run a counter; (middle) the state of the left key enables or disables the counter being translated into a sequencing of three lights for the left turn signal; (bottom) the state of the right key does the same for the right turn signals.

Two things to note: (1) the “lightsequencer” is a mysterious box that I implemented in Verilog; (2) the outputs of lightsequencer are put out to LED[2..0] for the left signal and LED[5..7] for the right signal. Notice the clever reversal of direction in the LED selection.

Lightsequencer – my Verilog code

 My Verilog code implements a simple table that converts a counted sequence into the pattern I want for the LEDs. For inputs of 00, 01, 10, 11, this function produces outputs of 000, 100, 110, and 111, which is what we need for the sequential lights on the turn signal.

module lightsequencer( enable, in3, out3 );input enable;input [2:0] in3;output [2:0] out3;assign out3[2] = in3[2]    && enable;assign out3[1] = &in3[2:1] && enable;assign out3[0] = &in3[2:0] && enable;endmodule 

Seeing is believing – my blinky

Here is a short video of the LED on the boards when running my FPGA program described above.

For blinking LEDs, controlling output pins, and otherwise using the FPGA as circuits, using schematics and HDL makes a lot of sense. When it’s time to write computational acceleration code, it sure is nice to have OpenCL as an option now.


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