Intel: Six-core chip to ship by second half '08

Intel announced Monday that it expects to ship a six-core processor to OEMs in the second half of this year.

With 1.9 billion transistors and 16MB of L3 cache, the six-core chip, code-named Dunnington, will be built with Intel's new 45 nanometer (nm) technology, according to Pat Gelsinger, a senior vice president and general manager of Intel's Digital Enterprise group.

"The big cache and six cores will give customers a nice bump in performance," Gelsinger said during a press briefing today to talk about the company's product roadmap and its upcoming Intel Developer's Forum slated to be held next month in Shanghai. "We're quite excited about it."

He said that the company plans to demonstrate the Dunnington chip at the developer's forum.

Dan Olds, an analyst with the Gabriel Consulting Group, said moving beyond quad-core processors, which to date has been the high-water mark in the semiconductor industry, is a major step -- one that keeps Intel well ahead of rival AMD. Just last week, AMD confirmed that it started shipping its triple-core Phenom processors.

"For AMD, it just means that they're falling a little bit further behind, unless they have some plans in the works that we're not privy to yet," added Olds. "A six-core is a big deal, but most desktop software can't really take advantage of dual-core yet, so this means that this chip is aimed directly at servers -- at least until consumer software gets better at multi-core threading."

Intel, which only moved to the 45nm process late last year, also announced Monday that it plans to start producing 32nm chips in either 2009 or 2010. Gelsinger said the first 32nm chip is slated to be a shrunken version of Nehalem, an upcoming four-core chip. The 32nm chips are code named Westmere.

During the press conference, Intel also said that it plans to start production of the Nehalem chips in the fourth quarter of this year. The 45nm Nehalem chips will include an integrated memory controller, eliminating the need for a front-side bus. Gelsinger explained that the new Nehalem architecture is modular, which means Intel should be able to build a chip using different building blocks while also enabling it to scale from two to eight cores.

Nehalem is also being designed to have two-way, simultaneous multi-threading, to use Intel's QuickPath interconnect, and to have a three-level cache hierarchy. Gelsinger said more information on the Nehalem specs will be disclosed at the Intel Developer's Forum.

Intel also reaffirmed to reporters that its upcoming Tukwila chip, an upgrade from the Itanium family, is due out by the end of the year.

Tukwila, a quad-core, 65nm processor, will run at up to 2 GHz, have dual-integrated memory controllers and use Intel's QuickPath interconnect instead of a front-side bus. The processor also will have 30MB of cache and 2 billion transistors on one chip.

"Development is proceeding quite smoothly," said Gelsinger.

And Gelsinger also updated information the company is giving out about Larrabee, an upcoming processor family that will have multiple cores and focus on high-end graphics applications. It also will sport a new cache architecture.

"At the time it was just a bunch of crazy people in the lab [working on multi-core research], but now we have real product development going on," said Gelsinger. "It will scale into teraflops on an individual chip."