If all things were equal and IBM made its systems as accessible as Dell and Hewlett-Packard do theirs, the IBM Power5 processor could bury Intel’s Itanium 2. First introduced last summer, the Power5 is a one-two punch, a triumph of engineering from a company that excels not only in processor design but also in the submicron science of chip manufacturing and packaging.
The Power5 is plenty fast, of course. But it can also be viewed as IBM’s first serious attempt to meet customers’ needs beyond speed. The Power5 offers improved power efficiency and terrific scalability, supports non-IBM operating systems (including Linux and Windows), and delivers partitioning and virtualization unmatched by current Intel technology.
The Power5 also foreshadows a new generation of 64-bit, PowerPC-based workstations and servers from IBM’s longtime partner in Power, Apple Computer. And IBM recently pulled an unexpected move for a company built on patents by publishing the Power architecture and tools under an open license.
There are so many ways in which Power5’s influence reaches beyond IBM’s primary base of well-heeled customers. Although IBM also sells Itanium 2, Opteron, and Xeon servers, the company seems clearly intent on putting Power5 systems in the hands of Linux and Windows administrators. Whether that makes sense will be up to customers, but the sheer technical muscle of Power5 and the faltering fortunes of the Itanium architecture demand IBM’s flagship processor take a trip under our microscope.
IBM has consistently attracted the brightest minds, the kind of engineers who deserve the moniker “computer scientist.” In the 1980s, these scientists cooked up a processor architecture that was built for performance: the IBM 801, the original RISC processor. The 801’s legacy lives on in the IBM Power series of enterprise-class processors.
The major difference between a RISC processor and a CISC processor, such as Intel’s x86, can be viewed as a tug-of-war between programmers and chip designers. CISC processors are designed to make application developers’ lives easier by reducing common operations to single, long-executing native instructions, giving CISC a reputation as a slow but friendly design. Compared in that light, RISC is fast and unfriendly. Each of its simple instructions serves a very narrow purpose, executes quickly, and parallelizes exceptionally well. RISC requires patient, gifted programmers and meticulously optimized compilers; RISC’s success attests to an abundance of both.
The best known Power5 attribute is its integration of two discrete RISC cores on a single chip. Announcements from AMD, Intel, and Sun Microsystems regarding upcoming multicore processors focused attention on this aspect of Power5, but multicore was also a feature of its predecessors, Power4 and Power4+. According to IBM, Power5 is fully compatible with Power4 executables. The wonder of multicore is that it delivers the pipe dream of more speed in less space without a marked increase in heat. But as you’ll see, multicore is not simply SMP on a chip.