For one, AMD will follow the RISC crowd with support for 3-Operand Instructions - up from two. So, unlike in the past where you would do A plus B and then have to store the result of the operation in A or B, developers can now store the result in a third location. This should reduce the total number of instructions needed to perform certain tasks and require less effort on the part of developers to keep track of registers.
The support for 3-Operand Instructions allows AMD to roll out a “fused multiply accumulate” instruction as well. This melds multiplication and addition to permit “iterative calculations with one instruction.”
Read the spec for yourself at http://developer.amd.com/sse5.jsp.
3 Penryns announced
The DailyTech is reporting details from Intel’s latest roadmap showing three Penryn-based Xeons with a 1600 MHz front-side bus.
The three new 1600 MHz front-side bus processors are available in dual-core and quad-core models. Quad-core Xeon E5472 and E5462 are the first quad-core models to receive the 1600 MHz front-side bus treatment.
(More on this enterprise HPC news item)
SGI reports Q4 results; posts loss
SGI reported its Q4 and Fiscal 2007 financial performance yesterday. A Reuters analysis shows that the company lost $36.9M in the quarter just ended, an increase of over $16M from its Q4 2006 lost of $20.4M.
But there is some good new; the company grew its core product sales by 27% in 2007, and 4th quarter GAAP revenue was up over 3rd quarter.
The company actually made dueling announcements. Its second press release was a retrospective highlighting recent acquisition wins and the progress of its technology strategy.