AMD using strained silicon on 90-nanometer chips

Advanced Micro Devices (AMD) will implement the strained silicon manufacturing technique on its upcoming 90-nanometer processors as well as 130-nanometer processors released this quarter, an AMD spokesman said Friday.

Strained silicon is a method used by chipmakers to widen the path through which electrons move across a chip. In most cases, a layer of silicon germanium is applied to a silicon wafer, and the reaction between the two substances stretches the gap between the atoms of the substances, allowing electrons to move more quickly through the chip. Details about AMD's strained silicon plans first appeared in The Semiconductor Reporter earlier this week.

Both Intel Corp. and IBM Corp. use the strained silicon technique to manufacture their 90-nanometer chips. IBM, like AMD, uses an additional technique called silicon on insulator (SOI) on its 90-nanometer chips.

SOI is a technique where transistors are built on top of a silicon wafer that has been coated with a layer of silicon oxide. This technique helps reduce the amount of current that leaks from the thin structures used at the 90-nanometer process generation, according to AMD and IBM.

AMD confirmed this week that it started shipping its 90-nanometer Oakville mobile processors to notebook manufacturers. Desktop and server processors based on the company's 90-nanometer process technology are expected later in the third quarter.

The transition to the 90-nanometer process generation has not gone as smoothly as many chipmakers would like, which is the usual state of affairs that the industry experiences about every two years when it shrinks the average size of a chip's features. However, AMD claims that it isn't suffering from any of the same transition problems that IBM and Intel experienced earlier this year.