Steve Weinger, senior manager for NAND flash marketing at Samsung Semiconductor Inc., said mobile phone video capabilities and the desire to store a never-ending stream of applications, movies, television shows and video clips from sites like YouTube.com is driving chip development and a 34 percent annual growth in sales. In fact, NAND flash chip memory has doubled in capacity in a little more than a year, he said.
"You could eventually have in the palm of your hand, all your movies, your pictures and everything else," he said. "I recently watched a football game on my iPhone with the DirectTV application. It was really crystal clear."
The problem, Weinger said, is that it's becoming difficult to make NAND flash memory denser.
Currently, the 25nm lithography being used by IMFT, a joint venture of Intel and Micron, is the smallest NAND production technique in existence. And an intel spokesman was cautious about how much smaller NAND flash memory can reliably get. That's important because smaller chips means more capacity in the same amount of space.
"The challenge of stepping down in lithography is to continue to provide equivalent performance...as previous products," Troy Winslow, director of NAND marketing at Intel, said in an interview with Computerworld . "Those were challenges we were able to overcome with this generation. But looking into the next couple of generations, we do recognize materials and process technology will have to change as obstacles mount."
Intel is already approaching atomic size with its lithography technique. Lithography is the process of creating cells and transistors in silicon, which are used to store bits of data. The smaller they are, the more data that can fit on a single NAND flash chip. At 25nm, the cells in silicon are 3,000 times thinner than a human strand of hair. And at that level inter-cell electrical interference becomes a tougher obstacle to tackle.
According to Michael Yang, a senior analyst for memory & storage with iSuppli Corp., anything smaller than 20nm lithography is uncharted territory for NAND flash.
"Unless it can be proven that [10-19] nanometer or lower is possible with NAND, it will be a crossroads for a new memory technology," Yang wrote in an e-mail response to Computerworld .
In addition, the number of electrons that can be stored in the memory cell decreases with each generation of flash memory, making it more difficult for the cells to reliably retain data, according to Wong.
Multi-level cell NAND, the most common type of flash memory used in consumer products, is in the midst of a transition from storing two bits of data per cell to storing three and four bits per cell. But additional bits per cell mean additional programming at the controller level order to ensure that each bit is accurately placed, Wong said. While programming for single-level cell (SLC) NAND is relatively simple, as only one bit can be placed in a cell, programming for two-bit and three-bit multi-level cell (MLC) NAND doubles or triples the coding required.
Increasing the number of bits per cell is not always the best answer. When IMFT released its 25nm NAND chip, the company's spokesman said in a Computerworld interview that the company had dropped production of a not-yet shipping three-bits-per-cell MLC NAND product because of reliability issues. That technology, announced last August , used IMFT's 34nm lithography process and represented an 11 percent reduction in NAND flash size.
"The major drawback of three-bit-per-cell technology is that it comes at the expense of performance and reliability," Kevin Kilbuck, director of NAND marketing at Micron, said.