Update: IBM, Sony, Toshiba unveil nine-core Cell processor

SAN FRANCISCO - Researchers from IBM, Sony and Toshiba unveiled the long-awaited Cell microprocessor Monday, revealing a multicore, multithreaded gaming engine described as "a supercomputer on a chip."

The three companies disclosed some of the first technical details about the four-year project at the International Solid State Circuits Conference here. Cell is expected to be the chip used in Sony's PlayStation 3 gaming console, and its performance should reach 10 times the capability of current PC processors, the companies said.

The prototype chip discussed Monday is comprised of one 64-bit Power PC processor core and eight separate processing cores that the companies call "synergistic processing elements," or SPEs. The cores can support multiple operating systems and programming models through the use of virtualization technologies, said Jim Kahle, director of technology at the Design Center for Cell Technology, and an IBM fellow.

Chip companies have turned to multicore designs in recent years as the performance of single-core processors has leveled off. A single-core processor can be set up to process multiple instruction threads at the same time, but must ultimately run faster and faster to improve its performance, which generates heat. Multicore processors can execute instructions in parallel, which means multiple separate instruction threads can be processed at the same time. By moving to multiple-core designs, chip designers can extract more performance from their products while reducing power consumption and heat dissipation.

The Cell designers have figured out how to push both frequency and parallelism, Kahle said. Cell is capable of running at more than 4.5GHz, but the companies have not determined how fast the final product will run. The chip will work with air-cooled designs similar to those used by the PlayStation 2, he said.

Cell will probably consume around 30 watts of power, similar to the Emotion Engine processor in the PlayStation 2 console, said Peter Glaskowsky, a technical analyst with The Envisioneering Group in Seaford, New York. This is also similar to the power consumption of Intel's Pentium M processor.

The dual-threaded PowerPC core functions as a control processor for the other eight single-threaded SPEs, which do the majority of the heavy lifting, Kahle said. The SPEs are designed for floating-point calculations, which are very important in graphics processing and supercomputer applications such as seismic modeling.

The SPEs have 256K bytes of cache memory on each core, while the PowerPC core uses 32K bytes of Level 1 cache and 512K bytes of Level 2 cache, said Masakazu Suzuoki, vice president of microprocessor development at Sony. Cache memory is used to store frequently accessed data close to the processor to avoid the delay associated with retrieving that data from the main memory.

The cores are held together by a shared bus that moves data into and out of the SPEs, Suzuoki said. Data is moved into and out of the chip with memory and I/O controllers that are integrated directly onto the processor, rather than implemented in a chipset.

Rambus Inc. designed both interfaces used in the Cell processor, said Rich Warmke, director of marketing for Rambus, in an interview prior to the Cell announcement. The memory interface uses Rambus' XDR (extreme data rate) standard, and the I/O interface uses the company's FlexIO technology, he said.