Here’s a collection of highlights, selected totally subjectively, from the recent enterprise HPC news stream as reported at insideHPC.com.
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HP leads blade market
From HPCwire this week
HP extended its lead in the worldwide blade server market in both total blade server units shipped and factory revenue, according to second calendar quarter 2007 server market figures released today by industry analyst firm IDC.
HP significantly increased its lead as the No. 1 blade server vendor in the period with 47.2 percent total factory revenue share, a year-over-year factory revenue growth rate of 71.9 percent.
This marks the 21st straight quarter with HP in the lead for units shipped. Interesting stat
In the highly competitive AMD Opteron processor-based server market segment, HP maintained its No. 1 position in both revenue and factory units shipped. Leading the competition in Intel and AMD x86-64-based servers, HP shipped more than 2.4 times and 22.3 times as many servers as IBM and Sun, respectively.
AMD marketing chief leaves PC industry
AMD announced this week that Chief Sales and Marketing Officer Henri Richard is leaving the company in September 2007. Word from The Register is that he’ll leave Sept 8, just 2 days before the Sept 10 launch of Barcelona. The Reg also reports that Richard is leaving the PC industry.
AMD’s spin is positive, but they company is having a hard time managing expectations and staying competitive, so this move could be a signal that they are finally serious about trying to turn things around.
Sun set to include transactional memory in Rock
Sun has confirmed that Rock, Sun’s next generation processor due out in the second half of 2008, will include transactional memory. (More on this enterprise HPC news item)
HP’s announcements at LinuxWorld
IT Director has a summary of HP’s announcements at the recently concluded LinuxWorld 2007.
Tilera’s 64-core mesh chip
There’s been a lot of discussion during my time away this week about the new product from Tilera, a 64-core chip aimed at embedded tasks like video, routers, and security processing.
The Silicon Valley-based start-up’s first product links together 64 RISC-like cores running at up to 1.0GHz. The real magic, however, stems from the five-lane switches used to link each core in an 8X8 grid that provides up to 32 terabits per second of data bandwidth across the whole chip. You end up with a product - Tile64 - that can tear through software threads.
…The mesh concept serves as a replacement for some of today’s processors that require a central bus to manage data traffic. Some companies have moved past the bus concept, in AMD’s case by creating its own high-speed interconnect called Hypertransport. Tilera extends that work by giving each core - or tile - five, independent networking lanes.
The company reportedly has 10 customers so far, but not everyone is ready to buy the early market hype.
John West summarizes the HPC news headlines every day at insideHPC.com, and writes on leadership and career issues for technology professionals at InfoWorld. You can contact him at firstname.lastname@example.org.