Here’s a collection of highlights, selected totally subjectively, from the recent enterprise HPC news stream as reported at insideHPC.com.
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IBM intro news cell blade aimed at strengthening enterprise adoption
IBM has announced the QS21 cell-based blade, replacing the QS20. The QS21 offers several improvements over the QS20. The new blade has two cell processors running at 3.2 GHz, supports up to 2 GB per processor (up from 1 GB), dual GbE ports and support for dual-port QDR InfiniBand fabrics.
The new QS21 is also smaller; 14 blades fit into a standard BladeCenter chassis, up from seven. The new configuration can cram 25 TFLOPS in a standard 42U rack.
(More on this enterprise HPC news item)
AMD improves hardware virtualization support
Story on the wires this week about AMD’s partnership with VMware to improve support for migration of virtual machines between different versions of AMD processors.
AMD-V Extended Migration provides the necessary support for virtualization software to mask the differences between CPU generations, facilitating the safe live migration of virtual machines between servers running different generations of AMD processors. This includes existing single-core and dual-core processors and all future AMD processor revisions, including the upcoming “Barcelona” Quad-Core AMD Opteron processors, the first native x86 quad-core microprocessor.
If you’re headed to SF in mid-September, AMD will be showcasing AMD-V Extended Migration using VMware at VMworld.
AMD announces ISA extensions for HPC
AMD announced this week they’re adding new instruction set extensions designed to improve performance in HPC, multimedia, and security apps.
The extensions, called SSE5, evolve the Streaming SIMD Extensions introduced originally in 1999. Although AMD is making the specification available starting today to foster a dialogue with developers, they won’t appear in product until AMD’s Bulldozer core is available in 2009. (Really? Bulldozer?)
The Register dug into the spec a little
For one, AMD will follow the RISC crowd with support for 3-Operand Instructions - up from two. So, unlike in the past where you would do A plus B and then have to store the result of the operation in A or B, developers can now store the result in a third location. This should reduce the total number of instructions needed to perform certain tasks and require less effort on the part of developers to keep track of registers.
The support for 3-Operand Instructions allows AMD to roll out a “fused multiply accumulate” instruction as well. This melds multiplication and addition to permit “iterative calculations with one instruction.”
Read the spec for yourself at http://developer.amd.com/sse5.jsp.
3 Penryns announced
The DailyTech is reporting details from Intel’s latest roadmap showing three Penryn-based Xeons with a 1600 MHz front-side bus.
The three new 1600 MHz front-side bus processors are available in dual-core and quad-core models. Quad-core Xeon E5472 and E5462 are the first quad-core models to receive the 1600 MHz front-side bus treatment.
(More on this enterprise HPC news item)
SGI reports Q4 results; posts loss
SGI reported its Q4 and Fiscal 2007 financial performance yesterday. A Reuters analysis shows that the company lost $36.9M in the quarter just ended, an increase of over $16M from its Q4 2006 lost of $20.4M.
But there is some good new; the company grew its core product sales by 27% in 2007, and 4th quarter GAAP revenue was up over 3rd quarter.
The company actually made dueling announcements. Its second press release was a retrospective highlighting recent acquisition wins and the progress of its technology strategy.
John West summarizes the HPC news headlines every day at insideHPC.com, and writes on leadership and career issues for technology professionals at InfoWorld. You can contact him at firstname.lastname@example.org.