Intel's new processors, multi-threaded networking, software, and pricing; NASA builds world's largest shared memory system; enterprise grids, and more

Today's enterprise HPC roundup turns out to be the Day of Intel with new processors at the high end, multi-threaded networking, an open-sourced thread library for C++, and a 50% price cut from Intel.

Oh, and other people did some stuff, too. Like NASA building the world's largest shared memory system, new developments in enterprise grids, and new storage from Isilon.

Here’s a collection of highlights, selected totally subjectively, from the recent enterprise HPC news stream as reported at

Univa and Sun team up for enterprise grids

Univa and Sun have announced [PDF] that they’ve signed a new agreement that allows OEM and support for Sun’s Grid Engine to be integrated into the Univa Globus Cluster Edition software, puts Univa into the Sun Partner Advantage Program (SPA), and starts co-marketing/co-sales efforts between the two companies.

Univa was started by Carl Kesselman, Ian Foster, and Steve Tuecke in 2004.

Intel aims at AMD’s margins, lowers prices

An article over at PCWorld reports that Intel has instituted targeted price drops of as much as 50% in a possible attempt to push even harder on AMD’s market share. Most of this is taking place on the desktop, not in HPC-class machines. But we can hope the competition will spill over. (More on this enterprise HPC news item)

Intel’s new network controllers

Intel has announced that they’ve added two new Ethernet controllers to their lineup. The 10 GbE and 1 GbE dual port controller address the needs of multi-core chips and server consolidation applications to push more bits out the door.

The announcement is reminiscent of Sun’s dual-port multithreaded networking announcement back in February of this year.

Intel open sources multi-threading library

Intel announced this week that they’re open sourcing Intel Threading Building Blocks (TBB), a C++ template library for creating parallel apps. The company seems to be positioning TBB as the way to parallelize C++ applications in a way that more closely matches the object-oriented ethos. Apparentl the jury is still out on whether TBB really brings anything new to the table, even among Intel's own software bloggers.

You can read more on this story, along with links to overviews of the library and other points of view, here at

Caneland: Intel’s new quad-core Xeon platform

Intel is blogging this week about the release of its new Xeon (codenamed Tigerton for crying out loud). The Xeon will be sold as the Quad-Core Xeon 7300 at 2.93GHz, and pushes Intel’s Core processor architecture to mid- and high-end servers. The chip has been shipping in limited quantities to customers since June and will move out in volume in the third quarter.

Caneland? That’s what you get when you combine the Tigerton processor with the Clarksboro chipset. sigh

Intel has a video interview with Kirk Skaugen, Intel vice president and General Manager of the Server Products Groupon, linked from the blog entry.

Kirk spoke openly and frankly and gave out quite a lot of new information; mentioning that Caneland has been shipping since June, talked about how we expect Caneland’s 16 cores to double the performance of our previous MP offering on some workloads. Kirk also gave glimpses into what to expect next year from Intel in this slice of the market.

(More on this HPC news item)

Isilon releases new storage systems

Isilon Systems has announced that they’ve released two new products in their storage lineup. The IQ 9000 and EX 9000 offerings scale up to 1.6 PB in a single file system and single volume. According to the company this development achieves “scalability levels 100 times that of traditional SAN and NAS systems.”

The new systems are being deployed by customers like the Comcast Entertainment Group, DailyMotion, KodakGallery and Photobox. (More on this enterprise HPC news item)

NASA builds world’s largest shared memory system

SGI and NASA announced this week that the agency is acquiring a 2,048 processor SGI Altix as part of its four phase procurement to replace Columbia, NASA’s earlier giant cluster of SGI machines. (Details on this HPC news item)

John West summarizes the HPC news headlines every day at, and writes on leadership and career issues for technology professionals at InfoWorld. You can contact him at