Chip wars go to the Core

Let me ask you: If your wildest dreams were realized, how many cores per CPU would you have in your servers, workstations and power desktops right now? How much Level 2 cache memory would you have in each core, or would you rather it be shared amongst the cores? Would you rather have memory controllers for each pair of cores that access a set-aside block of memory, or one memory controller that sees the entire address space?

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Oh, so that’s the sound of one million pages turning. I’ll wager that the majority of my certifiably savvy readership hasn’t given such nuts-and-bolts matters much thought. Well, Intel and AMD are giving it lots of thought right now, and I imagine the burning question at AMD is this: What do we do after AMD and Intel are matched at eight cores?

If I had a vote, I’d have both vendors stop at four cores and focus on fat and fast busses that give those cores something to fill instead of something to wait for. AMD and Intel both face bus bottlenecks, and that’s the bane of multi-core. Presently, dual-core CPUs from both chipmakers have to share memory and I/O buses that were designed to serve a single CPU core. Every time you add a core, contention for access to memory and peripherals rises, lowering the genuine performance benefit of the extra core. Even AMD’s laudable design can’t deliver near-linear performance gains from additional cores. AMD is revamping AMD64’s total design for quad-core so that even when cores get stuck in contention, the busses run so fast that the traffic clears quickly. AMD is taking a run at getting third-party vendors signed up to place their peripherals directly on its Hypertransport serial bus. If AMD can make that work, then, potentially, every core can have direct access to system peripherals. That would be a quantum leap for x86.

What worries me is that Intel might just go nuts bumping the number of cores, clock speed, cache and front-side bus speed while more or less hewing to today’s Core Microarchitecture in terms of key factors like bringing its memory and bus controllers on-chip. Let’s say that AMD wants to hold fast at quad or octo-core and work on perfecting the total system architecture so it can keep up. But what if Intel keeps cranking on core and gigahertz? While AMD is sledding along with eight cores, non-uniform memory architecture and direct on-core bus links from everything to everything in the system, Intel might ship a 16-way Core Microarchitecture CPU/chipset that looks more or less like Cloverdale 4-way, except for more—you guessed it—cache, gigahertz and cores.

The question is, how will AMD react? The buying public isn’t yet fully educated on the advantages that AMD64 has over Core Microarchitecture. When both chipmakers talk 64-bit computing and virtualization, my sense is that most buyers (not, I hope, my readers) take these to mean that AMD and Intel are in lock step. Not terribly long from now, AMD could find itself cornered into explaining to non-gearhead buyers why AMD64 stayed put at 8 cores and 3.8GHz when Intel announces sixteen core, five GHz Core Microarchitecture CPUs with 2.5GHz front-side buses. I want to tell AMD to keep to the high road and trust that the commercial market will come around as it did with Opteron. But I know that when before Intel runs its full-page ad in InfoWorld hawking its 16-way Core Microarchitecture CPU, the only CPU that can cram 32 cores into a 1U rack chassis, I’ll have to make sure you know what it all means. I don’t assume AMD will have the better story. But either way, if I have anything to say about it, you spend one nickel on gear based on cores, cache and clock. I’ll lay it all out on the table, fairly, in terms you’ll understand.