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Sun paints Niagara green for launch

Sun talks up talks up the new UltraSparc T1 chip's eco-friendly design

By China Martens, IDG News Service
November 14, 2005
 

Sun Microsystems  is due to take the wraps off its new UltraSparc T1 chip Monday. Previously code-named Niagara, the company's multithreaded, multicore processor had been slated to appear early in 2006. Unlike previous chip launches, Sun isn't planning to announce specifics on the servers the chip will power; instead the company is unveiling UltraSparc T1 on the day it talks up eco-friendly chip design at an event in San Francisco.

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With the company's typical flair for hyperbole in full swing, Sun is positioning the new chip as "the world's first eco-responsible processor" due to its low power consumption, according to an early company release. If only the world moved to embrace UltraSparc T1-based servers, carbon dioxide emissions would be greatly lowered and billions of dollars of savings would be realized in energy costs, the Sun release stated.

Details on pricing and the new line of Sun Fire servers that will be powered by the new processor will likely appear Dec. 6 at Sun's quarterly product launch in New York, according to Fred Kohout, vice president of marketing for Sun's scalable systems group. The UltraSparc T1 should ship in volume in the new servers before year-end, he said in a phone interview Thursday. Sun recently came under fire for delays in ramping up the volume of shipments of its Galaxy servers, which use Advanced Micro Devices' Opteron processor.

Kohout stressed the "clean-sheet" design of the UltraSparc T1, an effort Sun embarked on four years ago. "We've simplified the design point and increased the throughput at a very low power consumption," he said.

In an interview earlier this week in London, Sun Chairman and Chief Executive Officer Scott McNealy explained the early appearance of the new chip as a direct result of creating a brand-new design versus trying to re-engineer an existing processor. He also said that the UltraSparc T1 would use the same hardware as Galaxy.

"Niagara is the first purpose-built processor for the network services age," Kohout said. "It's the first 'rack on a chip.'"

The new chip incorporates Sun's patented CoolThreads multithreading technology and will be available in four-, six- and eight-core implementations running at a clock speed of either 1GHz or 1.2GHz, according to Kohout. The eight-core implementation will be able to process 32 different tasks simultaneously, he said, since each core can handle four software threads. The UltraSparc T1 consumes about 70 watts of power, much less than Intel's Xeon processors or IBM's Power chips, Kohout added. The Sun processor has four on-board memory controllers, he said.

"This is going to be a cross-over product," Kohout said, suggesting the new chip may have appeal to non-Sparc users. "Regardless of the vertical industry, they all have racks and racks of highly inefficient CPUs," he added. "UltraSparc T1 is the next consolidation engine."

"Power and cooling are key issues right now," Vernon Turner, group vice president and general manager of IDC's Enterprise Computing group, said, adding that the timing of Niagara's launch may draw interest from non-Sparc customers interested in lowering their utility bills.

Winning non-Sparc customers would "bring Sun the ability to upsell into Solaris and Java," Turner said. He did question Monday's launch, which occurs as Sun hosts a discussion on eco-friendly chip design in San Francisco. "It's unusual to have a product launch that's not about feeds and speeds," Turner said. Sun will be fielding its Chief Technology Officer Greg Papadopoulos and Marc Tremblay, vice president and chief architect of the company's scalable systems group at the event.

Sun is expected to relaunch itself into the blades market early next year. While he wouldn't be drawn on details, Kohout said that the UltraSparc T1 would be "a good fit in the blade space."


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• McNealy: Galaxy servers to ship in volume soon
• Sun's Niagara to use four on-chip memory controllers


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