Sun's Niagara to use four on-chip memory controllers

Sun Microsystems Inc.'s upcoming Niagara processor will use four on-board memory controllers to keep the multicore, multithreaded processor running at maximum efficiency, the company's head processor designer said Tuesday at the Fall Processor Forum.

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Sun has spent much of 2005 promoting its new x86 servers, but the company is pressing forward with aggressive multicore, multithreaded Sparc processors code-named Niagara and Rock, said Marc Tremblay, vice president and chief architect at Sun. The company plans to unveil servers based on Niagara starting early next year.

The first iteration of the Niagara family will be able to process 32 separate tasks at the same time, with eight processing cores capable of handling four software threads each. An integrated memory controller is crucial to that design, Tremblay said. Putting the memory controller -- which routes data between the processing cores and the memory -- on the processor allows the memory controller to run at the same frequency as the processor. This gets data into the chip as fast as it can be processed, improving chip efficiency.

In fact, four DDR2 (double data rate 2) memory controllers will be employed to keep Niagara's eight cores filled with data, Tremblay said. "In Niagara, with a minimum of 32 outstanding transactions, you better have a pretty high memory bandwidth," he said.

Keeping those cores constantly filled with data also allows Sun to use much smaller amounts of cache memory on Niagara as compared to the high-end processors Itanium 2 and Power 5 processors manufactured by Intel Corp. and IBM Corp., respectively, Tremblay said. Intel plans to use 24M bytes of cache on its forthcoming Montecito Itanium 2 processor, and IBM is using 36M bytes of cache on the Power 5 chip.

Cache memory stores data on the processor, instead of outside the chip in main memory. Chips without a fast connection to memory suffer when they have to leave the chip to find a piece of data. Niagara will feature just 3M bytes of cache memory, Tremblay said, which allows Sun to keep the eight-core Niagara processor small enough to maximize yields.

It also means that Niagara will be running flat out most of the time. One benefit of cache memory is that it consumes less power than other components on the processor. But with Niagara, Sun will eschew many of the dynamic power management techniques in development across the processor industry, Tremblay said.

This is possible because Niagara will only consume a maximum of 70 watts of power, Tremblay said. By contrast, Montecito will consume 100 watts of power under maximum operating conditions, which is less than the previous Itanium 2 processor.

Sun figures that Niagara might as well run as close to that 70 watt threshold as possible to ensure maximum performance, Tremblay said. Other chip makers use clock speed and voltage throttling techniques to shut off areas of a processor that are not in use, but when Niagara notices a drop-off in demand from one area of the chip it will switch the next thread in the queue to that area, he said.

Niagara will be at or near the top in most measurements of performance per watt, which is quickly becoming one of the most important performance metrics when evaluating a new server, Tremblay said.

REFERENCES:
Sun hopes to win back Wall St. with new servers, Sep. 11, 2005
Sun eyes throughput-computing push, Network World (US), Jul. 28, 2005